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Ognjen Glamocanin Ph.D.

Hardware Engineer
Synthara AG
ognjen.glamocanin@synthara.ai



About Me

I am a computer engineer, broadly interested in the world of post-Moore and LLM-era computer systems: from accelerator architectures for edge and low-power applications, to security of heterogeneous cloud-scale systems. Throughout my career, I have worked on many interesting problems in the post-Moore era, such as evaluating power consumption in early stages of CPU hardware design, machine learning acceleration, and security of reconfigurable hardware (FPGAs) in the cloud.

I am currently a hardware engineer at Synthara AG, working on integrating in-memory computation solutions into future generations of edge devices and SoCs, allowing low power and high performance for arithmetic-intensive workloads.

I hold a Ph.D. degree from the School of Computer and Communication Sciences, EPFL, where I worked at the Parallel Systems Architecture Laboratory PARSA with Dr. Mirjana Stojilovic and Prof. Babak Falsafi. My main research area was the hardware security of remote FPGAs, and I investigated how the pursuit of heterogeneity and better performance and can easily impact security. Specifically, my research focused on FPGAs, and how access to low-level reconfigurable hardware in the cloud can compromise and enhance security.

In addition to my Ph.D. degree from EPFL, I have a Computer Science Master's degree from the Faculty of Science and Engineering of the Sorbonne Université, for which I received a French government scholarship for international students. I obtained my Bachelor's degree in Electronics and Electrical Engineering from the University of Novi Sad.

I had multiple industry internships during my studies, including one at ARM France in 2018, where I investigated the impact of different elements of the CPU microarchitecture on power consumption and used ML to develop and integrate a power estimation model into a cycle-accurate CPU microarchitecture simulator. During my internship at Frobas in 2017, I was looking into ways to efficiently accelerate ML computation.

You can find the most recent version of my CV here.

Apart from my education and work, I am an AFOL (Adult Fan of LEGO), meaning that I am crazy about LEGOs and I love creating my own LEGO builds. You can find some of my cool builds here.

Work Experience

  1. Synthara AG
    Hardware Engieer
    September 2023–ongoing
  2. EPFL
    Doctoral Assistant and Ph.D. Student in FPGA Security
    Sep 2018– Aug 2023
  3. ARM France
    CPU Micro-Architecture and Design Internship
    Mar 2018– Aug 2018
  4. Frobas D.O.O.
    Machine Learning Hardware Acceleration Internship
    Nov 2016– Jun 2017
  5. Elsys Eastern Europe
    Hardware Functional Verification Internship
    Jul 2016– Oct 2016

Education

Ph.D. in Computer and Communication Sciences, EPFL

2018– 2023 (graduated August 29, 2023)

M.Sc. in Computer Science, Sorbonne Université, Paris VI

2017–2018

B.Sc. with Honours in Electrical Engineering, University of Novi Sad, FTN

2013–2017

Awards


Publications

  1. Instruction-Level Power Leakage Evaluation of Soft-Core CPUs on Shared FPGAs
    O. Glamocanin, S. Shrivastava, J. Yao, N. Ardo, M. Payer, and M. Stojilovic
    Springer Journal in Hardware and Systems Security, Special issue on Multitenant Computing Security Challenges and Solutions, 2023.
    Detailed Record PDF Code BibTex

  2. Active Wire Fences for Multi-Tenant FPGAs
    O. Glamocanin, Andjela Kostic, Stasa Kostic, and M. Stojilovic
    26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), May 3–5, 2023.
    Detailed Record PDF BibTex Best Paper Award Nomination

  3. RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks
    D. Spielmann*, O. Glamocanin*, and M. Stojilovic
    (* equal contribution)
    IACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES), September 10–14, 2023.
    Detailed Record PDF Code BibTex

  4. Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs
    O. Glamocanin, H. Bazaz, M. Payer, and M. Stojilovic
    The Design, Automation, and Test in Europe Conference and Exibition (DATE23), April 17–19, 2023.
    Detailed Record PDF BibTex

  5. The Side-Channel Metric Cheat Sheet
    K. Papagiannopoulos*, O. Glamocanin*, M. Azouaoui*, D. Ros*, F. Regazzoni*, and M. Stojilovic*
    (* equal contribution)
    ACM Computing Surveys, 2022.
    Detailed Record PDF Code BibTex

  6. Improving First-Order Threshold Implementations of SKINNY
    A. Caforio, D. Collins, O. Glamocanin, and S. Banik
    22nd International Conference on Cryptology in India (INDOCRYPT21), December 13–15, 2021.
    Detailed Record PDF BibTex

  7. Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks
    O. Glamocanin*, D. G. Mahmoud*, F. Regazzoni, and M. Stojilovic
    (* equal contribution)
    The Design, Automation, and Test in Europe Conference and Exibition (DATE21), February 1–5, 2021.
    Detailed Record PDF BibTex

  8. Are Cloud FPGAs Really Vulnerable to Power-Analysis Attacks?
    O. Glamocanin, L. Coulon, F. Regazzoni, and M. Stojilovic
    The Design, Automation, and Test in Europe Conference and Exibition (DATE20), March 9–13, 2020.
    Detailed Record PDF BibTex

  9. Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs
    O. Glamocanin, L. Coulon, F. Regazzoni, and M. Stojilovic
    The International Symposium on Field-Programmable Gate Arrays (ISFPGA20), February 23–25, 2020.
    Detailed Record PDF BibTex

Teaching

EPFL


University of Novi Sad, Faculty of Technical Sciences


Contact

Email

LinkedIn


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